/*
 * parameter tst
 */
module n_and (in1, in2, out);

parameter regsize = 8;

input in1, in2;
output out;

wire [regsize-1:0] in1, in2, out;
assign out = in1 & in2;

endmodule

module test_n_and;

reg [15:0] i16, ii16;
wire [15:0] o16;
reg [7: 0] i8, ii8;
wire [7:0] o8;

n_and #(16) and16 (i16, ii16, o16);
n_and and8 (i8, ii8, o8); //using default value here

initial begin
 $write("start");
 $strobe("i16 = %b ii16 = %b o16 = %b    |  i8 = %b ii8 = %b o8 = %b",
          i16, ii16, o16, i8, ii8, o8);
 i16 = 1;
 ii16 = 0;
 i8 = 0;
 ii8 = 1;
 #2;
end

always begin
 #1 ii16 = ~ii16;
    i8 = ~i8;
     $strobe("i16 = %b ii16 = %b o16 = %b    |  i8 = %b ii8 = %b o8 = %b",
          i16, ii16, o16, i8, ii8, o8);
 end

endmodule

